This invention relates to computer memory access systems generally, and particularly to systems which provide for fast sequential data access, useful in sequential computation operations such as multiply/accumulate operations required, for example, in neural network calculations.
In performing neural network calculations, a large number of multiply/accumulate operations are performed. Typically, a DSP (digital signal processor) is used to perform these calculations because it can complete a multiply and accumulate operation in a single memory access cycle (generally, within 75-125 nanoseconds). However, to provide a low cost, high performance neural network operation, a large sequentially accessed table of static weights (data values) must be available to the DSP. If the data values from this table, which is sequentially accessed, cannot be supplied within the access cycle time (i.e., within 75-125 nanoseconds), the DSP is obliged to wait for the data; in which event, the full speed of the DSP would not be utilized.
An SRAM (fast static random access memory) is capable of providing a DSP with data at a sufficiently fast rate (i.e., within 75-125 nanoseconds). However, an SRAM carries with it the disadvantages of high cost and high power dissipation.
What is needed and would be useful, therefore, is a lower cost system which could provide both fast memory access and fast multiply/accumulate operation, as would be required for example in neural network calculations.